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| 1995 data sheet the m pd75p0076 replaces the m pd750068s internal mask rom with a one-time prom and features expanded rom capacity. because the m pd75p0076 supports programming by users, it is suitable for use in prototype testing for system development using the m pd750064, 750066, and 750068 products, and for use in small-lot production. detailed information about function is provided in the following users manual. be sure to read it before designing: m pd750068 users manual: u10670e features compatible with m pd750068 memory capacity: ? prom : 16384 x 8 bits ? ram : 512 x 4 bits can operate with same power supply voltage as the mask rom version m pd750068 v dd = 1.8 to 5.5 v on-chip a/d converter capable of low-voltage operation (av ref = 1.8 to 5.5 v) 8-bit resolution x 8 channels small shrink sop package ordering information part number package m pd75p0076cu 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) m pd75p0076gt 42-pin plastic shrink sop (375 mil, 0.8-mm pitch) caution on-chip pull-up resistors by mask option cannot be provided. document no. u10232ej1v0ds00 (1st edition) date published december 1996 n printed in japan m pd75p0076 mos integrated circuit 4-bit single-chip microcontroller the information in this document is subject to change without notice. the mark shows major revised points.
m pd75p0076 2 functional outline parameter function instruction execution time ? 0.95, 1.91, 3.81, 15.3 m s (@ 4.19 mhz with main system clock) ? 0.67, 1.33, 2.67, 10.7 m s (@ 6.0 mhz with main system clock) ? 122 m s (@ 32.768 khz with subsystem clock) on-chip memory prom 16384 x 8 bits ram 512 x 4 bits general-purpose register ? 4-bit operation: 8 x 4 banks ? 8-bit operation: 4 x 4 banks input/ cmos input 12 connections of on-chip pull-up resistors can be specified by software: 7 output also used for analog input pins: 4 port cmos input/output 12 connections of on-chip pull-up resistors can be specified by software: 12 also used for analog input pins: 4 n-ch open-drain 8 13-v withstand voltage input/output pins total 32 timer 4 channels ? 8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter) ? 8-bit basic interval timer/watchdog timer: 1 channel ? watch timer: 1 channel serial interface ? 3-wire serial i/o mode msb or lsb can be selected for transferring first bit ? 2-wire serial i/o mode a/d converter 8-bit resolution x 8 channels (1.8 v av ref v dd ) bit sequential buffer 16 bits clock output (pcl) ? f , 1.05 mhz, 262 khz, 65.5 khz (@ 4.19 mhz with main system clock) ? f , 1.5 mhz, 375 khz, 93.8 khz (@ 6.0 mhz with main system clock) buzzer output (buz) ? 2, 4, 32 khz (@ 4.19 mhz with main system clock or @ 32.768 khz with subsystem clock) ? 2.93, 5.86, 46.9 khz (@ 6.0 mhz with main system clock) vectored interrupts external: 3, internal: 4 test input external: 1, internal: 1 system clock oscillator ? ceramic or crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation standby function stop/halt mode operating ambient temperature t a = C40 to +85 ?c power supply voltage v dd = 1.8 to 5.5 v package ? 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) ? 42-pin plastic shrink sop (375 mil, 0.8-mm pitch) m pd75p0076 3 contents 1. pin configuration (top view) ................................................................................................. .. 4 2. block diagram ................................................................................................................ ............ 5 3. pin functions ................................................................................................................ ............... 6 3.1 port pins ................................................................................................................... ................................ 6 3.2 non-port pins ............................................................................................................... ............................ 7 3.3 equivalent circuits for pins ................................................................................................ .................... 9 3.4 handling of unused pins ..................................................................................................... .................... 12 4. switching between mk i and mk ii modes ............................................................................ 13 4.1 difference betweens mk i mode and mk ii mode ................................................................................ .... 13 4.2 setting of stack bank selection (sbs) register .............................................................................. ...... 14 5. differences between m pd75p0076 and m pd750064, 750066 and 750068 ........................ 15 6. memory configuration ......................................................................................................... ... 16 7. instruction set .............................................................................................................. ............. 18 8. one-time prom (program memory) write and verify .................................................... 29 8.1 operation modes for program memory write/verify ............................................................................. 29 8.2 steps in program memory write operation ..................................................................................... ....... 30 8.3 steps in program memory read operation ...................................................................................... ...... 31 8.4 one-time prom screening ..................................................................................................... ................ 32 9. electrical specifications.................................................................................................... .. 33 10. characteristics curves (reference values) ................................................................ 49 11. package drawings ............................................................................................................ ........ 51 12. recommended soldering conditions ................................................................................. 53 appendix a differences among m pd75068, 750068 and 75p0076 ......................................... 54 appendix b development tools ................................................................................................. 55 appendix c related documents ................................................................................................. 58 m pd75p0076 4 1. pin configuration (top view) ? 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) m pd75p0076cu ? 42-pin plastic shrink sop (375 mil, 0.8-mm pitch) m pd75p0076gt pin identification an0 to an7 : analog input 0 to 7 p110 to p113 : port 11 av ref : analog reference pcl : programmable clock av ss : analog ground pto0, pto1 : programmable timer output 0, 1 buz : buzzer clock reset : reset input d0 to d7 : data bus 0 to 7 sb0, sb1 : serial data bus 0, 1 int0, int1, int4 : external vectored interrupt 0, 1, 4 sck : serial clock int2 : external test input 2 si : serial input kr0 to kr3 : key return so : serial output md0 to md3 : mode selection 0 to 3 ti0, ti1 : timer input 0, 1 p00 to p03 : port 0 v dd : positive power supply p10 to p13 : port 1 v pp : programmable power supply p20 to p23 : port 2 v ss : ground p30 to p33 : port 3 x1, x2 : main system clock oscillation 1, 2 p40 to p43 : port 4 xt1, xt2 : subsystem clock oscillation 1, 2 p50 to p53 : port 5 p60 to p63 : port 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 xt1 xt2 reset x1 x2 p33/md3 p32/md2 p31/md1 p30/md0 av ss p63/kr3/an7 p62/kr2/an6 p61/kr1/an5 p60/kr0/an4 p113/an3 p112/an2 p111/an1 p110/an0 av ref v pp v dd v ss p40/d0 p41/d1 p42/d2 p43/d3 p50/d4 p51/d5 p52/d6 p53/d7 p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p10/int0 p11/int1 p12/ti1/int2 p13/ti0 p20/pto0 p21/pto1 p22/pcl p23/buz in normal operation mode, make sure to connect v pp directl y to v dd . m pd75p0076 5 2. block diagram basic interval timer/watchdog timer watch timer 8-bit timer/ event counter#0 8-bit timer/ event counter#1 cascaded 16-bit timer/ event counter clocked serial interface interrupt control a/d converter intbt intw intt0 intw intt1 tout0 intcsi buz/p23 ti0/p13 pto0/p20 ti1/p12/int2 pto1/p21 si/sb1/p03 so/sb0/p02 sck/p01 int0/p10 int1/p11 int4/p00 int2/p12/ti1 kr0/p60 to kr3/p63 an0/p110 to an3/p113 an4/p60 to an7/p63 av ref av ss cy sp (8) sbs bank program counter program memory (prom) 16384 x 8 bits decode and control general reg. data memory (ram) 512 x 4bits port0 port1 port2 port3 port4 port5 port6 port11 bit seq. buffer (16) p00 to p03 4 4 4 4 4 4 p10 to p13 p20 to p23 p30/md0 to p33/md3 p40/d0 to p43/d3 p50/d4 to p53/d7 p60 to p63 p110 to p113 fx/2 n cpu clock f clock output control clock divider sub main system clock generator stand by control pcl/p22 xt1 xt2 x1 x2 v pp v dd v ss reset alu 4 4 4 4 4 m pd75p0076 6 3. pin functions 3.1 port pins pin name i/o alternate function function 8-bit after i/o circuit accessible reset type note 1 p00 i int4 this is a 4-bit input port (port0). not input for p01 to p03, on-chip pull-up resistors are available p01 i/o sck software-specifiable in 3-bit units. m pd75p0076 7 3.2 non-port pins (1/2) pin name i/o alternate function function after circuit reset type note ti0 i p13 inputs external event pulses to the timer/event input -c ti1 p12/int2 counter. pto0 o p20 timer/event counter output input e-b pto1 p21 pcl p22 clock output buz p23 optional frequency output (for buzzer output or system clock trimming) sck i/o p01 serial clock i/o input m pd75p0076 8 3.2 non-port pins (2/2) pin name i/o alternate function function after circuit reset type md0 to md3 i p30 to 33 mode selection for program memory (prom) input e-b write/verify. d0 to d3 i/o p40 to 43 data bus pin for program memory (prom) write/verify. input m-e d4 to d7 p50 to 53 v pp note programmable voltage supply in program memory (prom) write/verify mode. in normal operation mode, connect directly to v dd . apply +12.5 v in prom write/verify mode. v dd positive power supply v ss ground note during normal operation, the v pp pin will not operate normally unless connected to v dd pin. m pd75p0076 9 3.3 equivalent circuits for pins the equivalent circuits for the m pd75p0076s pin are shown in schematic diagrams below. in v dd p-ch n-ch v dd p-ch n-ch out data output disable in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type a v dd p-ch p.u.r. enable p.u.r. p.u.r. : pull-up resistor in v dd p-ch in/out p.u.r. enable data p.u.r. type d output disable p.u.r. : pull-up resistor type b cmos standard input buffer push-pull output that can be set to high impedance output (with both p-ch and n-ch off). schmitt trigger input with hysteresis characteristics. type a type d (1/3) type e-b type b type b-c type f-a schmitt trigger input with hysteresis characteristics. m pd75p0076 10 output disable (p) output disable data output disable (n) p.u.r. enable p-ch p.u.r. in/out p-ch n-ch v dd v dd p.u.r. : pull-up resistor type f-b type y in p-ch n-ch v dd v dd av ss av ss input enable reference voltage (from the voltage tap of the serial resistor string) type y-a input butfer type a type y in type m-c input instruction (+13 v withstand voltage) p-ch p.u.r. note v dd p.u.r. : pull-up resistor type m-e* in instruction sampling c output disable data n-ch in/out note this is a pull-up resistor which only operates when an input instruction is executed (when the pin is low a current flows from v dd to the pin). output disable data p.u.r. enable p-ch p.u.r. in/out n-ch v dd + (2/3) voltage control circuit (+13 v withstand voltage) m pd75p0076 11 type z-n p.u.r. enable p.u.r. v dd p-ch in/out p.u.r.: pull-up resistor type y-d data output disable type y type d type b aden reference voltage av ref n-ch av ss (3/3) m pd75p0076 12 3.4 handling of unused pins pin recommended connection p00/int4 connect to v ss or v dd p01/sck independently connect to v ss or v dd through p02/so/sb0 resistor p03/si/sb1 connected to v ss p10/int0, p11/int1 connect to v ss or v dd p12/ti1/int2 p13/ti0 p20/pto0 input mode : independently connected to v ss p21/pto1 or v dd through resistor p22/pcl output mode : open p23/buz p30/md0 to p33/md3 p40/d0 to p43/d3 connected to v ss p50/d4 to p53/d7 p60/kr0/an4 to p63/kr3/an7 input mode : independently connected to v ss or v dd through resistor output mode : open p110/an0 to p113/an3 connected to v ss or v dd xt1 note connect to v ss or v dd xt2 note open v pp make sure to connect directly to v dd av ref connect to v ss av ss note when the subsystem clock is not used, set sos.0 = 1 (on-chip feedback resistor is not used). m pd75p0076 13 4. switching between mk i and mk ii modes setting a stack bank selection (sbs) register for the m pd75p0076 enables the program memory to be switched between the mk i mode and the mk ii mode. this capability enables the evaluation of the m pd750064, 750066, and 750068 using the m pd75p0076. when the sbs bit 3 is set to 1: sets mk i mode (corresponds to mk i mode of m pd750064, 750066, and 750068) when the sbs bit 3 is set to 0: sets mk ii mode (corresponds to mk ii mode of m pd750064, 750066, and 750068) 4.1 differences between mk i mode and mk ii mode table 4-1 lists the differences between the mk i mode and the mk ii mode of the m pd75p0076. table 4-1. differences between mk i mode and mk ii mode item mk i mode mk ii mode program counter pc 13 to 0 program memory (bytes) 16384 data memory (bits) 512 x 4 stack stack bank selectable from memory banks 0 and 1 stack bytes 2 bytes 3 bytes instruction bra !addr1 not provided provided calla !addr1 instruction call !addr 3 machine cycles 4 machine cycles execution time callf !faddr 2 machine cycles 3 machine cycles supported mask rom versions and mk i mode of m pd750064, 750066, mk ii mode of m pd750064, 750066, mode and 750068 and 750068 caution the mk ii mode supports a program area which exceeds 16k bytes in the 75x and 75xl series. this mode enhances the software compatibility with products which have more than 16k bytes. when the mk ii mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the mk i mode. furthermore, when a call !addr, or callf !faddr instruction is used, each instruction takes another machine cycle. therefore, when more importance is attached to ram utilization or throughput than software compatibility, use the mk i mode. m pd75p0076 14 4.2 setting of stack bank selection (sbs) register use the stack bank selection register to switch between the mk i mode and the mk ii mode. figure 4-1 shows the format for doing this. the stack bank selection register is set using a 4-bit memory manipulation instruction. when using the mk i mode, be sure to initialize the stack bank selection register to 100xb note at the beginning of the program. when using the mk ii mode, be sure to initialize it to 000xb note . note set the desired value for x. figure 4-1. format of stack bank selection register cautions 1. sbs3 is set to 1 after reset input, and consequently the cpu operates in the mk i mode. when using instructions for the mk ii mode, set sbs3 to 0 to enter the mk ii mode before using the instructions. 2. when using the mk ii mode, execute a subroutine call instruction and an interrupt instruction after reset input and after setting the stack bank selection register. sbs3 sbs2 sbs1 sbs0 f84h address 3 2 1 0 sbs 0 0 1 1 0 1 0 1 symbol stack area specification memory bank 0 memory bank 1 0 be sure to enter ? for bit 2. 0 1 mk ii mode mk i mode mode selection specification setting prohibited m pd75p0076 15 5. differences between m pd75p0076 and m pd750064, 750066 and 750068 the m pd75p0076 replaces the internal mask rom in the m pd750064, 750066, and 750068 with a one-time prom and features expanded rom capacity. the m pd75p0076s mk i mode supports the mk i mode in the m pd750064, 750066, and 750068 and the m pd75p0076s mk ii mode supports the mk ii mode in the m pd750064, 750066, and 750068. table 5-1 lists differences among the m pd75p0076 and the m pd750064, 750066, 750068. be sure to check the differences between corresponding versions beforehand, especially when a prom version is used for debugging or prototype testing of application systems and later the corresponding mask rom version is used for full-scale production. for further description of cpu functions and internal hardware, see the m pd750064 and 750068 preliminary product information (u10165e) . table 5-1. differences between m pd75p0076 and m pd750064, 750066, 750068 item m pd750064 m pd750066 m pd750068 m pd75p0076 program counter 12-bit 13-bit 14-bit program memory (bytes) mask rom mask rom mask rom one-time prom 4096 6144 8192 16384 data memory (x 4 bits) 512 mask options pull-up resistor for yes (on-chip specifiable) no (off chip) ports 4 and 5 wait time when yes (2 17 /f x , 2 15 /f x selectable) note no (fixed at 2 15 /f x ) note reset feedback resistor of yes (use/not use selectable) no (use) subsystem clock pin configuration pins 6 to 9 p33 to p30 p33/md3 to p30/md0 pin 20 ic v pp pins 34 to 37 p53 to p50 p53/d7 to p53/d4 pins 38 to 41 p43 to p40 p43/d3 to p40/d0 other noise resistance and noise radiation may differ due to different circuit complexities and mask layouts. note 2 17 /f x is 21.8 ms in 6.0 mhz operation and 31.3 ms in 4.19 mhz operation. 2 15 /f x is 5.46 ms in 6.0 mhz operation and 7.81 ms in 4.19 mhz operation. caution noise resistance and noise radiation are different in prom version and mask rom versions. if using a mask rom version instead of the prom version for processes between prototype development and full production, be sure to fully evaluate the cs of the mask rom version (not es). m pd75p0076 16 6. memory configuration figure 6-1. program memory map note can be used only in mk ii mode. remark for instructions other than those noted above, the br pcde and br pcxa instructions can be used to branch to addresses with changes in the pcs lower 8 bits only. mbe mbe mbe mbe mbe mbe mbe rbe rbe rbe rbe rbe rbe rbe internal reset start address (upper 6 bits) internal reset start address (lower 8 bits) intbt/int4 start address (upper 6 bits) intbt/int4 start address (lower 8 bits) int0 start address (upper 6 bits) int0 start address (lower 8 bits) int1 start address (upper 6 bits) int1 start address (lower 8 bits) intcsi start address (upper 6 bits) intcsi start address (lower 8 bits) intt0 start address (upper 6 bits) intt0 start address (lower 8 bits) intt1 start address (upper 6 bits) intt1 start address (lower 8 bits) reference table for geti instruction 0000h 0002h 0004h 0006h 0008h 000ah 000ch 0020h 007fh 0080h 07ffh 0800h 0fffh 1000h 1fffh 2000h 2fffh 3000h 3fffh callf !faddr instruction entry address branch address for the following instructions call !addr instruction subroutine entry address br $addr instruction relative branch address (?5 to ?, +2 to +16) brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address note note 76 0 ?br bcde ?br bcxa ?br !addr ?bra !addr1 ?calla !addr1 branch destination address specified by geti instruction, subroutine entry address m pd75p0076 17 figure 6-2. data memory map note either memory bank 0 or 1 can be selected as the stack area. (32 x 4) 256 x 4 (224 x 4) 256 x 4 128 x 4 0 1 15 000h 01fh 020h 0ffh 100h 1ffh f80h fffh general register area data area static ram (512 x 4) stack area note peripheral hardware area data memory memory bank unimplemented m pd75p0076 18 7. instruction set (1) representation and coding formats for operands in the instructions operand area, use the following coding format to describe operands corresponding to the instructions operand representations (for further description, see the ra75x assembler package users manualClanguage (eeu- 1363) ). when there are several codes, select and use just one. uppercase letters, and + and C symbols are key words that should be entered as they are. for immediate data, enter an appropriate numerical value or label. instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for further description, see the m pd750068 users manual (u10670e) ). labels that can be entered for fmem and pmem are restricted. representation coding format reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hlC, de, dl rpa1 de, dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h to fbfh, ff0h to fffh immediate data or label pmem fc0h to fffh immediate data or label addr 0000h to 3fffh immediate data or label addr1 000h to 3fffh immediate data or label (in mk ii mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h to 7fh immediate data (however, bit0 = 0) or label portn port0 to port6, port11 iexxx iebt, iecsi, iet0, iet1, ie0 to ie2, ie4, iew rbn rb0 to rb3 mbn mb0, mb1, mb15 note when processing 8-bit data, only even addresses can be specified. m pd75p0076 19 (2) operation legend a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register x : x register xa : register pair (xa); 8-bit accumulator bc : register pair (bc) de : register pair (de) hl : register pair (hl) xa : expansion register pair (xa) bc : expansion register pair (bc) de : expansion register pair (de) hl : expansion register pair (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag rbe : register bank enable flag portn : port n (n = 0 to 6, 11) ime : interrupt master enable flag ips : interrupt priority select register iexxx : interrupt enable flag rbs : register bank select register mbs : memory bank select register pcc : processor clock control register . : delimiter for address and bit (xx) : contents of address xx xxh : hexadecimal data m pd75p0076 20 (3) description of symbols used in addressing area remarks 1. mb indicates access-enabled memory banks. 2. in area *2, mb = 0 for both mbe and mbs. 3. in areas *4 and *5, mb = 15 for both mbe and mbs. 4. areas *6 to *11 indicate corresponding address-enabled areas. mb = 0 (000h to 07fh) mb = 15 (f80h to fffh) mb = mbs mbs = 0, 1, 15 mb = mbe ?mbs mbs = 0, 1, 15 *1 mb = 0 *2 mbe = 1 : mbe = 0 : *3 mb = 15, fmem = fb0h to fbfh, ff0h to fffh mb = 15, pmem = fc0h to fffh addr = 0000h to 3fffh *4 *5 *6 addr, addr1 = *7 (current pc) ?5 to (current pc) ? (current pc) +2 to (current pc) +16 *8 caddr = 0000h to 0fffh (pc 13 , 12 = 00b) or 1000h to 1fffh (pc 13 , 12 = 01b) or 2000h to 2fffh (pc 13 , 12 = 10b) or 3000h to 3fffh (pc 13 , 12 = 11b) faddr = 0000h to 07ffh taddr = 0020h to 007fh addr1 = 0000h to 3fffh (mk ii mode only) *9 *10 *11 program memory addressing data memory addressing m pd75p0076 21 (4) description of machine cycles s indicates the number of machine cycles required for skipping of skip-specified instructions. the value of s varies as shown below. ? no skip .......................................................................... s = 0 ? skipped instruction is 1-byte or 2-byte instruction ......... s = 1 ? skipped instruction is 3-byte instruction note ................... s = 2 note 3-byte instructions: br !addr, bra !addr1, call !addr, calla !addr1 caution the geti instruction is skipped for one machine cycle. one machine cycle equals one cycle (= t cy ) of the cpu clock f . use the pcc setting to select among four cycle times. m pd75p0076 22 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition transfer mov a, #n4 1 1 a ? n4 string-effect a reg1, #n4 2 2 reg1 ? n4 xa, #n8 2 2 xa ? n8 string-effect a hl, #n8 2 2 hl ? n8 string-effect b rp2, #n8 2 2 rp2 ? n8 a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l + 1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? l C 1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 @hl, a 1 1 (hl) ? a*1 @hl, xa 2 2 (hl) ? xa *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 mem, a 2 2 (mem) ? a*3 mem, xa 2 2 (mem) ? xa *3 a, reg1 2 2 a ? reg1 xa, rp 2 2 xa ? rp reg1, a 2 2 reg1 ? a rp1, xa 2 2 rp1 ? xa xch a, @hl 1 1 a ? (hl) *1 a, @hl+ 1 2 + s a ? (hl), then l ? l + 1 *1 l = 0 a, @hlC 1 2 + s a ? (hl), then l ? l C 1 *1 l = fh a, @rpa1 1 1 a ? (rpa1) *2 xa, @hl 2 2 xa ? (hl) *1 a, mem 2 2 a ? (mem) *3 xa, mem 2 2 xa ? (mem) *3 a, reg1 1 1 a ? reg1 xa, rp 2 2 xa ? rp table movt xa, @pcde 1 3 xa ? (pc 13-8 + de) rom reference xa, @pcxa 1 3 xa ? (pc 13-8 + xa) rom xa, @bcde 1 3 xa ? (bcde) rom note *11 xa, @bcxa 1 3 xa ? (bcxa) rom note *11 note as for the b register, only the lower 2 bits are valid. m pd75p0076 23 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition bit transfer mov1 cy, fmem.bit 2 2 cy ? (fmem.bit) *4 cy, pmem.@l 2 2 cy ? (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy ? (h + mem 3-0 .bit) *1 fmem.bit, cy 2 2 (fmem.bit) ? cy *4 pmem.@l, cy 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? cy *5 @h + mem.bit, cy 2 2 (h + mem 3-0 .bit) ? cy *1 operation adds a, #n4 1 1 + s a ? a + n4 carry xa, #n8 2 2 + s xa ? xa + n8 carry a, @hl 1 1 + s a ? a + (hl) *1 carry xa, rp 2 2 + s xa ? xa + rp carry rp1, xa 2 2 + s rp1 ? rp1 + xa carry addc a, @hl 1 1 a, cy ? a + (hl) + cy *1 xa, rp 2 2 xa, cy ? xa + rp + cy rp1, xa 2 2 rp1, cy ? rp1 + xa + cy subs a, @hl 1 1 + s a ? a C (hl) *1 borrow xa, rp 2 2 + s xa ? xa C rp borrow rp1, xa 2 2 + s rp1 ? rp1 C xa borrow subc a, @hl 1 1 a, cy ? a C (hl) C cy *1 xa, rp 2 2 xa, cy ? xa C rp C cy rp1, xa 2 2 rp1, cy ? rp1 C xa C cy and a, #n4 2 2 a ? a ^ n4 a, @hl 1 1 a ? a ^ (hl) *1 xa, rp 2 2 xa ? xa ^ rp rp1, xa 2 2 rp1 ? rp1 ^ xa or a, #n4 2 2 a ? avn4 a, @hl 1 1 a ? av(hl) *1 xa, rp 2 2 xa ? xavrp rp1, xa 2 2 rp1 ? rp1vxa xor a, #n4 2 2 a ? av n4 a, @hl 1 1 a ? av (hl) *1 xa, rp 2 2 xa ? xav rp rp1, xa 2 2 rp1 ? rp1v xa m pd75p0076 24 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition accumulator rorc a 1 1 cy ? a 0 , a 3 ? cy, a n-1 ? a n manipulate not a 2 2 a ? a increment/ incs reg 1 1 + s reg ? reg + 1 reg = 0 decrement rp1 1 1 + s rp1 ? rp1 + 1 rp1 = 00h @hl 2 2 + s (hl) ? (hl) + 1 *1 (hl) = 0 mem 2 2 + s (mem) ? (mem) + 1 *3 (mem) = 0 decs reg 1 1 + s reg ? reg C 1 reg = fh rp 2 2 + s rp ? rp C 1 rp = ffh compare ske reg, #n4 2 2 + s skip if reg = n4 reg = n4 @hl, #n4 2 2 + s skip if (hl) = n4 *1 (hl) = n4 a, @hl 1 1 + s skip if a = (hl) *1 a = (hl) xa, @hl 2 2 + s skip if xa = (hl) *1 xa = (hl) a, reg 2 2 + s skip if a = reg a = reg xa, rp 2 2 + s skip if xa = rp xa = rp carry flag set1 cy 1 1 cy ? 1 manipulate clr1 cy 1 1 cy ? 0 skt cy 1 1 + s skip if cy = 1 cy = 1 not1 cy 1 1 cy ? cy m pd75p0076 25 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition memory bit set1 mem.bit 2 2 (mem.bit) ? 1*3 manipulate fmem.bit 2 2 (fmem.bit) ? 1*4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 1*5 @h + mem.bit 2 2 (h + mem 3-0 .bit) ? 1*1 clr1 mem.bit 2 2 (mem.bit) ? 0*3 fmem.bit 2 2 (fmem.bit) ? 0*4 pmem.@l 2 2 (pmem 7-2 + l 3-2 .bit(l 1-0 )) ? 0*5 @h + mem.bit 2 2 (h + mem 3-0 .bit) ? 0*1 skt mem.bit 2 2 + s skip if(mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2 + s skip if(fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 *5 (pmem.@l) = 1 @h + mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 1 *1 (@h+mem.bit) = 1 skf mem.bit 2 2 + s skip if(mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2 + s skip if(fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 0 *5 (pmem.@l) = 0 @h + mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 0 *1 (@h+mem.bit) = 0 sktclr fmem.bit 2 2 + s skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@l 2 2 + s skip if(pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 and clear *5 (pmem.@l) = 1 @h + mem.bit 2 2 + s skip if(h + mem 3-0 .bit) = 1 and clear *1 (@h+mem.bit) = 1 and1 cy, fmem.bit 2 2 cy ? cy ^ (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cy ^ (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy ? cy ^ (h + mem 3-0 .bit) *1 or1 cy, fmem.bit 2 2 cy ? cyv(fmem.bit) *4 cy, pmem.@l 2 2 cy ? cyv(pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy ? cyv(h + mem 3-0 .bit) *1 xor1 cy, fmem.bit 2 2 cy ? cyv (fmem.bit) *4 cy, pmem.@l 2 2 cy ? cyv (pmem 7-2 + l 3-2 .bit(l 1-0 )) *5 cy, @h + mem.bit 2 2 cy ? cyv (h + mem 3-0 .bit) *1 m pd75p0076 26 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition branch br note 1 addr pc 13-0 ? addr *6 assembler selects the most appropriate instruction among the following: ? br !addr ? brcb !caddr ? br $addr addr1 pc 13-0 ? addr1 *11 assembler selects the most appropriate instruction among the following: ? bra !addr1 ? br !addr ? brcb !caddr ? br $addr1 !addr 3 3 pc 13-0 ? addr *6 $addr 1 2 pc 13-0 ? addr *7 $addr1 1 2 pc 13-0 ? addr1 pcde 2 3 pc 13-0 ? pc 13-8 + de pcxa 2 3 pc 13-0 ? pc 13-8 + xa bcde 2 3 pc 13-0 ? bcde note 2 *6 bcxa 2 3 pc 13-0 ? bcxa note 2 *6 bra note 1 !addr1 3 3 pc 13-0 ? addr1 *11 brcb !caddr 2 2 pc 13-0 ? pc 13, 12 + caddr 11-0 *8 notes 1. double boxes indicate support for the mk ii mode only. other areas indicate support for the mk i mode only. 2. as for the b register, only the lower 2 bits are valid. m pd75p0076 27 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition subroutine calla note !addr1 3 3 (sp C 6)(sp C 3)(sp C 4) ? pc 11-0 *11 stack control (sp C 5) ? 0, 0, pc 13,12 (sp C 2) ? x, x, mbe, rbe pc 13-0 ? addr1, sp ? sp C 6 call note !addr 3 3 (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 *6 (sp C 3) ? mbe, rbe, pc 13, 12 pc 13-0 ? addr, sp ? sp C 4 4 (sp C 6)(sp C 3)(sp C 4) ? pc 11-0 (sp C 5) ? 0, 0, pc 13, 12 (sp C 2) ? x, x, mbe, rbe pc 13-0 ? addr, sp ? sp C 6 callf note !faddr 2 2 (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 *9 (sp C 3) ? mbe, rbe, pc 13, 12 pc 13-0 ? 000 + faddr, sp ? sp C 4 3 (sp C 6)(sp C 3)(sp C 4) ? pc 11-0 (sp C 5) ? 0, 0, pc 13, 12 (sp C 2) ? x, x, mbe, rbe pc 13-0 ? 000 + faddr, sp ? sp C 6 ret note 1 3 mbe, rbe, pc 13, 12 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) sp ? sp + 4 x, x, mbe, rbe ? (sp + 4) pc 11-0 ? (sp)(sp + 3)(sp + 2) 0, 0, pc 13, 12 ? (sp + 1) sp ? sp + 6 rets note 1 3 + s mbe, rbe, pc 13, 12 ? (sp + 1) unconditional pc 11-0 ? (sp)(sp + 3)(sp + 2) sp ? sp + 4 then skip unconditionally x, x, mbe, rbe ? (sp + 4) pc 11-0 ? (sp)(sp + 3)(sp + 2) 0, 0, pc 13, 12 ? (sp + 1) sp ? sp + 6 then skip unconditionally reti 1 3 mbe, rbe, pc 13, 12 ? (sp + 1) pc 11-0 ? (sp)(sp + 3)(sp + 2) psw ? (sp + 4)(sp + 5), sp ? sp + 6 0, 0, pc 13, 12 ? sp + 1 pc 11-0 ? (sp)(sp + 3)(sp + 2) psw ? (sp + 4)(sp + 5), sp ? sp + 6 note double boxes indicate support for the mk ii mode only. other areas indicate support for the mk i mode only. m pd75p0076 28 group mnemonic operand no. of machine operation addressing skip bytes cycle area condition subroutine push rp 1 1 (sp C 1)(sp C 2) ? rp, sp ? sp C 2 stack control bs 2 2 (sp C 1) ? mbs, (sp C 2) ? rbs, sp ? sp C 2 pop rp 1 1 rp ? (sp + 1)(sp), sp ? sp + 2 bs 2 2 mbs ? (sp + 1), rbs ? (sp), sp ? sp + 2 interrupt ei 2 2 ime(ips.3) ? 1 control iexxx 2 2 iexxx ? 1 di 2 2 ime(ips.3) ? 0 iexxx 2 2 iexxx ? 0 i/o in note 1 a, portn 2 2 a ? portn (n = 0 to 6, 11) xa, portn 2 2 xa ? portn + 1 , portn (n = 4) out note 1 portn, a 2 2 portn ? a (n = 2 to 6) portn, xa 2 2 portn + 1 , portn ? xa (n = 4) cpu control halt 2 2 set halt mode (pcc.2 ? 1) stop 2 2 set stop mode (pcc.3 ? 1) nop 1 1 no operation special sel rbn 2 2 rbs ? n (n = 0 to 3) mbn 2 2 mbs ? n (n = 0, 1, 15) geti note 2, 3 taddr 1 3 ? when using tbr instruction *10 pc 13-0 ? (taddr) 5-0 + (taddr + 1) ? when using tcall instruction (sp C 4)(sp C 1)(sp C 2) ? pc 11-0 (sp C 3) ? mbe, rbe, pc 13, 12 pc 13-0 ? (taddr) 5-0 + (taddr + 1) sp ? sp C 4 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr + 1) instructions instruction 1 3 ? when using tbr instruction *10 pc 13-0 ? (taddr) 5-0 + (taddr + 1) 4 ? when using tcall instruction (sp C 6)(sp C 3)(sp C 4) ? pc 11-0 (sp C 5) ? 0, 0, pc 13, 12 (sp C 2) ? x, x, mbe, rbe pc 13-0 ? (taddr) 5-0 + (taddr + 1) sp ? sp C 6 3 ? when using instruction other than determined by tbr or tcall referenced execute (taddr)(taddr + 1) instructions instruction notes 1. before executing the in or out instruction, set mbe to 0 or 1 and set mbs to 15. 2. tbr and tcall instructions are assembler pseudo-instructions for the geti instructions table definitions. 3. double box indicates support for the mk ii mode only. other areas indicate support for the mk i mode only. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - m pd75p0076 29 8. one-time prom (program memory) write and verify the program memory in the m pd75p0076 is a 16384 x 8-bit electronic write-enabled one-time prom. the pins listed in the table below are used for this proms write/verify operations. clock input from the x1 pins is used instead of address input as a method for updating addresses. pin name function v pp pin (usually v dd ) where programming voltage is applied during program memory write/verify x1, x2 clock input pin for address updating during program memory write/verify. input the x1 pins inverted signal to the x2 pin. md0 to md3 operation mode selection pin for program memory write/verify d0/p40 to d3/p43 (lower 4) 8-bit data i/o pin for program memory write/verify d4/p50 to d7/p53 (upper 4) v dd pin where power supply voltage is applied. power voltage range for normal operation is 1.8 to 5.5 v. apply 6 v for program memory write/verify. caution pins not used for program memory write/verify should be handled as follows. ? all unused pins except xt2 ...... connect to vss via a pull-down resistor ? xt2 pin ........................................ leave open 8.1 operation modes for program memory write/verify when +6 v is applied to the m pd75p0076s v dd pin and +12.5 v is applied to its v pp pin, program memory write/verify modes are in effect. furthermore, the following detailed operation modes can be specified by setting pins md0 to md3 as shown below. operation mode specification operation mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l zero-clear program memory address l h h h write mode l l h h verify mode h x h h program inhibit mode x: l or h m pd75p0076 30 8.2 steps in program memory write operation high-speed program memory write can be executed via the following steps. (1) pull down unused pins to v ss via resistors. set the x1 pin to low. (2) apply +5 v to the v dd and v pp pins. (3) wait 10 m s. (4) zero-clear mode for program memory addresses. (5) apply +6 v to v dd and +12.5 v to v pp . (6) write data using 1-ms write mode. (7) verify mode. if write is verified, go to step (8) and if write is not verified, go back to steps (6) to (7). (8) x [= number of write operations from steps (6) to (7)] x 1 ms additional write (9) 4 pulse inputs to the x1 pin updates (increments +1) the program memory address. (10) repeat steps (6) to (9) until the last address is completed. (11) zero-clear mode for program memory addresses. (12) apply +5 v to the v dd and v pp pins. (13) power supply off the following diagram illustrates steps (2) to (9). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 x repetitions write verify additional write address increment data input data output data input m pd75p0076 31 8.3 steps in program memory read operation the m pd75p0076 can read out the program memory contents via the following steps. (1) pull down unused pins to v ss via resistors. set the x1 pin to low. (2) apply +5 v to the v dd and v pp pins. (3) wait 10 m s. (4) zero-clear mode for program memory addresses. (5) apply +6 v to v dd and +12.5 v to v pp . (6) verify mode. when a clock pulse is input to the x1 pin, data is output sequentially to one address at a time based on a cycle of four pulse inputs. (7) zero-clear mode for program memory addresses. (8) apply +5 v to the v dd and v pp pins. (9) power supply off the following diagram illustrates steps (2) to (7). v pp v dd v dd + 1 v dd v pp v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 data output data output md0/p30 md2/p32 md3/p33 md1/p31 ? m pd75p0076 32 8.4 one-time prom screening due to its structure, the one-time prom cannot be fully tested before shipment by nec. therefore, nec recommends the screening process, that is, after the required data is written to the prom and the prom is stored under the high- temperature conditions shown below, the prom should be verified. storage temperature storage time 125 ?c 24 hours m pd75p0076 33 9. electrical specifications absolute maximum ratings (t a = 25?c) parameter symbol test conditions rating unit power supply voltage v dd C0.3 to +7.0 v prom power supply v pp C0.3 to +13.5 v voltage input voltage v i1 except ports 4, 5 C0.3 to v dd +0.3 v v i2 ports 4, 5 (n-ch open drain) C0.3 to +14 v output voltage v o C0.3 to v dd +0.3 v output current high i oh per pin C10 ma total of all pins C30 ma output current low i ol per pin 30 ma total of all pins 220 ma operating ambient t a C40 to +85 ?c temperature storage temperature t stg C65 to +150 ?c caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability of the product may be impaired. the absolute maximum ratings are values that may physically damage the products. be sure to use the products within the ratings. capacitance (t a = 25?c,v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf output capacitance c out unmeasured pins returned to 0 v. 15 pf i/o capacitance c io 15 pf m pd75p0076 34 main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter test conditions min. typ. max. unit ceramic oscillation 1.0 6.0 note 2 mhz resonator frequency (fx) note 1 oscillation after v dd reaches oscil- 4 ms stabilization time note 3 lation voltage range min. crystal oscillation 1.0 6.0 note 2 mhz resonator frequency (fx) note 1 oscillation v dd = 4.5 to 5.5 v 10 ms stabilization time note 3 30 external x1 input 1.0 6.0 note 2 mhz clock frequency (fx) note 1 x1 input 83.3 500 ns high-/low-level width (t xh , t xl ) notes 1. the oscillation frequency and x1 input frequency indicate characteristics of the oscillator only. for the instruction execution time, refer to ac characteristics. 2. when the power supply voltage is 1.8 v v dd < 2.7 v and the oscillation frequency is 4.19 mhz < fx 6.0 mhz, setting the processor clock control register (pcc) to 0011 results in 1 machine cycle being less than the required 0.95 m s. therefore, set pcc to a value other than 0011. 3. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd or releasing the stop mode. caution when using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. x1 x2 x2 x1 c1 c2 x2 x1 c1 c2 m pd75p0076 35 xt1 xt2 subsystem clock oscillator characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) resonator recommended constant parameter test conditions min. typ. max. unit crystal oscillation 32 32.768 35 khz resonator frequency (f xt ) note 1 oscillation v dd = 4.5 to 5.5 v 1.0 2 s stabilization time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 xt1 input high-/low-level 515 m s width (t xth , t xtl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. the oscillation stabilization time is necessary for oscillation to stabilize after applying v dd . caution when using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. the subsystem clock oscillator is designed as a low amplification circuit to provide low consumption current, causing misoperation by noise more frequently than the main system clock oscillation circuit. special care should therefore be taken for wiring method when the subsystem clock is used. xt2 xt1 c4 c3 r m pd75p0076 36 recommended oscillation circuit constants ceramic resonator (t a = C20 to +80 ?c) frequency oscillation circuit oscillation voltage manufacturer product name (mhz) constants (pf) range (v dd ) remarks c1 c2 min. max. murata mfg. csb1000j note 1.0 100 100 2.2 5.5 rd = 5.6 k w co., ltd. csa2.00mg040 2.0 100 100 2.0 cst2.00mg040 with on-chip capacitor csa4.00mg 4.0 30 30 1.8 cst4.00mgw with on-chip capacitor csa4.19mg 4.19 30 30 cst4.19mgw with on-chip capacitor csa6.00mg 6.0 30 30 2.6 cst6.00mgw with on-chip capacitor csa6.00mgu 30 30 1.8 cst6.00mgwu with on-chip capacitor note when the csb1000j (1.0 mhz) manufactured by murata mfg. is used as a ceramic resonator, a limiting resistor (rd = 5.6 k w ) is required (see the figure below). other recommended resonators do not require such a limiting resistor. x2 x1 csb1000j c2 c1 rd caution the oscillation circuit constants and oscillation voltage range only indicate the conditions under which the circuit can oscillate stably, and do not guarantee the oscillation frequency accuracy. if oscillation frequency accuracy is required in the actual circuit, it is necessary to adjust oscillation frequencies in the actual circuit, and you should consult directly with the manufacturer of the resonator used. m pd75p0076 37 dc characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit output current low i ol per pin 15 ma total of all pins 150 ma input voltage high v ih1 ports 2, 3, and 11 2.7 v dd 5.5 v 0.7v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0.8v dd v dd v 1.8 v dd < 2.7 v 0.9v dd v dd v v ih3 ports 4, 5 2.7 v dd 5.5 v 0.7v dd 13 v (n-ch open-drain) 1.8 v dd < 2.7 v 0.9v dd 13 v v ih4 x1, xt1 v dd C 0.1 v dd v input voltage low v il1 ports 2-5, 11 2.7 v dd 5.5 v 0 0.3v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il2 ports 0, 1, 6, reset 2.7 v dd 5.5 v 0 0.2v dd v 1.8 v dd < 2.7 v 0 0.1v dd v v il3 x1, xt1 0 0.1 v output voltage high v oh sck, so, ports 2, 3, 6 i oh = C1.0 ma v dd C 0.5 v output voltage low v ol1 sck, so, ports 2-6 i ol = 15 ma, 0.2 2.0 v v dd = 4.5 to 5.5 v i ol = 1.6 ma 0.4 v v ol2 sb0, sb1 when n-ch open-drain 0.2v dd v pull-up resistor 3 1 k w input leakage i lih1 v in = v dd pins other than x1, xt1 3 m a current high i lih2 x1, xt1 20 m a i lih3 v in = 13 v ports 4, 5 (n-ch open-drain) 20 m a input leakage i lil1 v in = 0 v ports 4, 5, pins other than x1, xt1 C3 m a current low i lil2 x1, xt1 C20 m a ports 4, 5 (n-ch open-drain) C3 m a when input instruction is not executed i lil3 ports 4, 5 (n-ch open- C30 m a drain) when input v dd = 5.0 v C10 C27 m a instruction is executed v dd = 3.0 v C3 C8 m a output leakage i loh1 v out = v dd sck, so/sb0, sb1, ports 2, 3, 6 3 m a current high i loh2 v out = 13 v ports 4, 5 (n-ch open-drain) 20 m a output leakage i lol v out = 0 v C3 m a current low on-chip pull-up resistor r l v in = 0 v ports 0-3, 6 (excluding p00 pin) 50 100 200 k w m pd75p0076 38 dc characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit supply current note 1 i dd1 6.0 mhz note 2 v dd = 5.0 v 10% note 3 3.4 10.2 ma crystal oscillation v dd = 3.0 v 10% note 4 0.8 2.4 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.9 2.7 ma v dd = 3.0 v 10% 0.5 1.5 ma i dd1 4.19 mhz note 2 v dd = 5.0 v 10% note 3 2.7 7.4 ma crystal oscillation v dd = 3.0 v 10% note 4 0.6 1.8 ma i dd2 c1 = c2 = 22 pf halt mode v dd = 5.0 v 10% 0.8 2.4 ma v dd = 3.0 v 10% 0.4 1.2 ma i dd3 32.768 khz note 5 low-voltage v dd = 3.0 v 10% 42 126 m a crystal oscillation mode note 6 v dd = 2.0 v 10% 23 69 m a v dd = 3.0 v, t a = 25?c 42 84 m a low current con- v dd = 3.0 v 10% 40 120 m a sumption mode note 7 v dd = 3.0 v, t a = 25?c 40 80 m a i dd4 halt mode low- v dd = 3.0 v 10% 824 m a voltage v dd = 2.0 v 10% 412 m a mode note 6 v dd = 3.0 v, t a = 25?c 816 m a low current v dd = 3.0 v 10% 721 m a consumption v dd = 3.0 v, 714 m a mode note 7 t a = 25?c i dd5 xt1 = 0 v v dd = 5.0 v 10% 0.05 10 m a stop mode note 8 v dd = 3.0 v 0.02 5.0 m a 10% t a = 25?c 0.02 3.0 m a notes 1. not including currents flowing in on-chip pull-up resistors. 2. including oscillation of the subsystem clock. 3. when the processor clock control register (pcc) is set to 0011 and the device is operated in the high-speed mode. 4. when pcc is set to 0000 and the device is operated in the low-speed mode. 5. when the system clock control register (scc) is set to 1001 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 6. when the sub-oscillation circuit control register (sos) is set to 0000. 7. when sos is set to 0010. 8. when sos is set to 00 1, the feedback resistors of the sub-oscillation circuit is cutoff. ( : dont care) m pd75p0076 39 ac characteristics (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cpu clock cycle t cy operating on v dd = 2.7 to 5.5 v 0.67 64 m s time note 1 main system clock 0.95 64 m s (minimum instruction execution operating on 114 122 125 m s time = 1 machine cycle) subsystem clock ti0, ti1 input f ti v dd = 2.7 to 5.5 v 0 1.0 mhz frequency 0 275 khz ti0, ti1 input t tih , t til v dd = 2.7 to 5.5 v 0.48 m s high-/low-level width 1.8 m s interrupt input high-/ t inth , t intl int0 im02 = 0 note 2 m s low-level width im02 = 1 10 m s int1, 2, 4 10 m s kr0 to kr3 10 m s reset low-level width t rsl 10 m s notes 1. the cycle time (minimum instruction execution time) of the cpu clock ( f ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (scc) and the processor clock control register (pcc). the figure at the right indicates the cycle time t cy versus supply voltage v dd characteristic with the main system clock operating. 2. 2t cy or 128/fx is set by setting the interrupt mode register (im0). 1 023456 0.5 1 3 2 4 5 6 60 64 supply voltage v dd [v] t cy vs v dd (at main system clock operation) cycle time t cy [ s] m guaranteed operation range m pd75p0076 40 serial transfer operation 2-wire and 3-wire serial i/o mode (sck...internal clock output): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy1 v dd = 2.7 to 5.5 v 1300 ns 3800 ns sck high-/low-level t kl1 , t kh1 v dd = 2.7 to 5.5 v t kcy1 /2C50 ns width t kcy1 /2C150 ns si note 1 setup time t sik1 v dd = 2.7 to 5.5 v 150 ns (to sck - ) 500 ns si note 1 hold time t ksi1 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 output t kso1 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 250 ns delay time c l = 100 pf note 2 0 1000 ns notes 1. in 2-wire serial i/o mode, read sb0 or sb1 instead. 2. r l and c l are the load resistance and load capacitance of the so output lines. 2-wire and 3-wire serial i/o mode (sck...external clock input): (t a = C40 to +85?c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy2 v dd = 2.7 to 5.5 v 800 ns 3200 ns sck high-/low-level t kl2 , t kh2 v dd = 2.7 to 5.5 v 400 ns width 1600 ns si note 1 setup time t sik2 v dd = 2.7 to 5.5 v 100 ns (to sck - ) 150 ns si note 1 hold time t ksi2 v dd = 2.7 to 5.5 v 400 ns (from sck - ) 600 ns sck ? so note 1 output t kso2 r l = 1 k w ,v dd = 2.7 to 5.5 v 0 300 ns delay time c l = 100 pf note 2 0 1000 ns notes 1. in 2-wire serial i/o mode, read sb0 or sb1 instead. 2. r l and c l are the load resistance and load capacitance of the so output lines. m pd75p0076 41 a/d converter characteristics (t a = C40 to +85 ?c, v dd = 1.8 to 5.5 v, 1.8 v av ref v dd ) parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit absolute accuracy note 1 v dd = av ref 2.7 v dd 1.5 lsb 1.8 v v dd < 2.7 v 3 lsb v dd 1 av ref 3 lsb conversion time note 2 t conv 168/f x m s sampling time note 3 t samp 44/f x m s analog input voltage v ian av ss av ref v analog input impedance r an 1000 m w av ref current i ref 0.25 2.0 ma notes 1. absolute accuracy excluding quantization error ( 1/2 lsb). 2. time after execution of conversion start instruction until completion of conversion (eoc = 1) (40.1 m s: in f x = 4.19 mhz operation) 3. time after conversion start instruction until completion of sampling (10.5 m s: in f x = 4.19 mhz operation) m pd75p0076 42 ac timing test point (excluding x1, xt1 input) clock timing ti0, ti1 timing x1 input 1/f x t xl t xh 0.1 v v dd ?.1 v xt1 input 1/f xt t xtl t xth 0.1 v v dd ?.1 v v ih (min.) v il (max.) v ih (min.) v il (max.) v oh (min.) v ol (max.) v oh (min.) v ol (max.) ti0, ti1 1/f ti t til t tih m pd75p0076 43 t kcy1, 2 t kl1, 2 t kh1, 2 sck si so t sik1, 2 t ksi1, 2 t kso1, 2 input data output data t kso1, 2 t sik1, 2 t kl1, 2 t kh1, 2 sck t ksi1, 2 sb0, 1 t kcy1, 2 serial transfer timing 3-wire serial i/o mode 2-wire serial i/o mode m pd75p0076 44 interrupt input timing reset input timing t rsl reset t intl t inth int0, 1, 2, 4 kr0 to 3 m pd75p0076 45 data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85?c) parameter symbol test conditions min. typ. max. unit release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 15 /f x ms wait time note 1 release by interrupt request note 2 ms notes 1. the oscillation stabilization wait time is the time during which the cpu operation is stopped to prevent unstable operation at the oscillation start. 2. depends on the basic interval timer mode register (btm) settings (see the table below). btm3 btm2 btm1 btm0 wait time fx = at 4.19 mhz fx = at 6.0 mhz 0002 20 /fx (approx. 250 ms) 2 20 /fx (approx. 175 ms) 0112 17 /fx (approx. 31.3 ms) 2 17 /fx (approx. 21.8 ms) 1012 15 /fx (approx. 7.81 ms) 2 15 /fx (approx. 5.46 ms) 1112 13 /fx (approx. 1.95 ms) 2 13 /fx (approx. 1.37 ms) m pd75p0076 46 data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal) v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr t srel t wait t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr m pd75p0076 47 dc programming characteristics (t a = 25 5?c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol test conditions min. typ. max. unit input voltage high v ih1 except x1, x2 0.7v dd v dd v v ih2 x1, x2 v dd C0.5 v dd v input voltage low v il1 except x1, x2 0 0.3v dd v v il2 x1, x2 0 0.4 v input leakage current i li v in = v il or v ih 10 m a output voltage high v oh i oh = C1 ma v dd C1.0 v output voltage low v ol i ol = 1.6 ma 0.4 v v dd power supply current i dd 30 ma v pp power supply current i pp md0 = v il , md1 = v ih 30 ma cautions 1. avoid exceeding +13.5 v for v pp including the overshoot. 2. v dd must be applied before v pp , and cut after v pp . ac programming characteristics (t a = 25 5?c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol note 1 test conditions min. typ. max. unit address setup time note 2 (to md0 )t as t as 2 m s md1 setup time (to md0 )t m1s t oes 2 m s data setup time (to md0 )t ds t ds 2 m s address hold time note 2 (from md0 - )t ah t ah 2 m s data hold time (from md0 - )t dh t dh 2 m s md0 -? data output float delay time t df t df 0 130 ns v pp setup time (to md3 - )t vps t vps 2 m s v dd setup time (to md3 - )t vds t vcs 2 m s initial program pulse width t pw t pw 0.95 1.0 1.05 ms additional program pulse width t opw t opw 0.95 21.0 ms md0 setup time (to md1 - )t m0s t ces 2 m s md0 ? data output delay time t dv t dv md0 = md1 = v il 1 m s md1 hold time (from md0 - )t m1h t oeh t m1h + t m1r 3 50 m s2 m s md1 recovery time (from md0 )t m1r t or 2 m s program counter reset time t pcr C10 m s x1 input high-/low-level width t xh , t xl C 0.125 m s x1 input frequency f x C 4.19 mhz initial mode set time t i C2 m s md3 setup time (to md1 - )t m3s C2 m s md3 hold time (from md1 )t m3h C2 m s md3 setup time (to md0 )t m3sr C during program memory read 2 m s address note 2 ? data output delay time t dad t acc during program memory read 2 m s address note 2 ? data output hold time t had t oh during program memory read 0 130 ns md3 hold time (from md0 - )t m3hr C during program memory read 2 m s md3 ? data output float delay time t dfr C during program memory read 2 m s notes1. corresponding symbol of m pd27c256a 2. the internal address signal is incremented by 1 at the rising edge of the fourth x1 input and is not connected to the pin. m pd75p0076 48 program memory write timing program memory read timing t vps t vds v pp v dd v dd +1 v dd v pp v dd t xh t xl t had t dad t dv t i t m3hr t dfr t pcr t m3sr x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 data output data output t vps t vds t xh t xl t i t ds t dh t dv t df t ds t dh t ah t as t pw t m1r t m0s t opw t m1s t m1h t pcr t m3s t m3h data input data output data input data input v pp v dd v dd +1 v dd v pp v dd x1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 m pd75p0076 49 10. characteristics curves (reference values) 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 (t a = 25 c) supply voltage v dd (v) supply current i dd (ma) pcc = 0010 pcc = 0001 pcc = 0000 main system clock halt mode + 32-khz oscillation xt1 xt2 x1 x2 crystal resonator 6.0 mhz crystal resonator 32.768 khz 330 k w 22 pf 22 pf 33 pf 33 pf i dd vs v dd (main system clock: 6.0-mhz crystal resonator) pcc = 0011 subsystem clock halt mode (sos.1 = 0) and main system clock stop mode + 32-khz oscillation (sos.1 = 0) subsystem clock halt mode (sos.1 = 1) and main system clock stop mode + 32-khz oscillation (sos.1 = 1) subsystem clock operation mode (sos.1 = 0) m pd75p0076 50 10 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 xt1 xt2 x1 x2 crystal resonator 4.19 mhz crystal resonator 32.768 khz 330 k w 22 pf 22 pf 33 pf 33 pf supply voltage v dd (v) supply current i dd (ma) pcc = 0010 main system clock halt mode + 32-khz oscillation subsystem clock halt mode (sos.1 = 0) and main sysyem clock stop mode + 32-khz oscillation (sos.1 = 0) subsystem clock operation mode (sos.1 = 0) i dd vs v dd (main system clock: 4.19-mhz crystal resonator) (t a = 25 c) main system clock stop mode + 32-khz oscillation (sos.1 = 1) pcc = 0001 pcc = 0000 pcc = 0011 subsystem clock halt mode (sos.1 = 1) and m pd75p0076 51 11. package drawings 42pin plastic shrink dip (600 mil) item millimeters inches a b c f g h i j k 39.13 max. 1.778 (t.p.) 3.2 0.3 0.51 min. 4.31 max. 1.78 max. 0.17 15.24 (t.p.) 5.08 max. n 0.9 min. r 1.541 max. 0.070 max. 0.035 min. 0.126 0.012 0.020 min. 0.170 max. 0.200 max. 0.600 (t.p.) 0.007 0.070 (t.p.) p42c-70-600a-1 a c d g notes 1) each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. d 0.50 0.10 0.020 m 0.25 0.010 +0.10 ?.05 0~15 0~15 +0.004 ?.003 +0.004 ?.005 m k n l 13.2 0.520 2) item "k" to center of leads when formed parallel. 42 1 22 21 l m r b f h j i m pd75p0076 52 42 pin plastic shrink sop (375 mil) 121 a 42 22 detail of lead end c m m n b d e f g i j h k l 3 +7 ? s42gt-80-375b-1 item millimeters inches a b c d f g h i j k l 18.16 max. 0.8 (t.p.) 2.9 max. 2.5 0.2 10.3 0.3 1.13 max. 0.715 max. 0.005 0.003 0.115 max. 0.406 0.281 0.044 max. note m n 0.10 0.8 0.2 1.6 0.2 7.15 0.2 0.004 0.031 +0.009 ?.008 each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 0.063 0.008 0.098 0.031 (t.p.) 0.15 0.006 0.10 0.004 0.014 0.35 0.125 0.075 +0.004 ?.002 +0.009 ?.008 +0.10 ?.05 +0.004 ?.003 e +0.012 ?.013 +0.009 ?.008 +0.10 ?.05 m pd75p0076 53 12. recommended soldering conditions the m pd75p0076 should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 12-1. surface mounting type soldering conditions m pd75p0076gt: 42-pin plastic shrink sop (375 mil, 0.8 mm pitch) soldering soldering conditions symbol method infrared reflow package peak temperature: 235?c, time: 30 seconds or less (at 210?c or higher), ir35-00-2 number of reflow processes: twice or less vps package peak temperature: 215?c, time: 40 seconds or less (at 200?c or higher), vp15-00-2 number of reflow processes: twice or less wave soldering solder temperature: 260?c or below, time: 10 seconds or less, number of flow ws60-00-1 process: 1, preheating temperature: 120?c or below (package surface temperature) partial heating pin temperature: 300?c or below, time : 3 seconds or less (per device side) caution use of more than one soldering method should be avoided (except for partial heating). table 12-2. insertion type soldering conditions m pd75p0076cu: 42-pin plastic shrink dip (600 mil, 1.778 mm pitch) soldering method soldering conditions wave soldering (pins only) solder bath temperature: 260 ?c or less, time: 10 seconds or less partial heating pin temperature: 300 ?c or below, time: 3 seconds or less (per device side) caution ensure that the application of wave soldering is limited to the pins and no solder touches the main unit directly. m pd75p0076 54 appendix a differences among m pd75068, 750068 and 75p0076 parameter m pd75068 m pd750068 m pd75p0076 program memory mask rom mask rom one-time prom 0000h to 1f7fh 0000h to 1fffh 0000h to 3fffh (8064 x 8 bits) (8192 x 8 bits) (16384 x 8 bits) data memory 000h to 1ffh (512 x 4 bits) cpu 75x standard cpu 75xl cpu general-purpose register 4 bits x 8 or 8 bits x 4 (4 bits x 8 or 8 bits x 4) x 4 banks instruction when main system 0.95, 1.91, 15.3 m s ? 0.67, 1.33, 2.67, 10.7 m s (during 6.0-mhz operation) execution clock is selected (during 4.19-mhz operation) ? 0.95, 1.91, 3.81, 15.3 m s (during 4.19-mhz operation) time when subsystem 122 m s (during 32.768-khz operation) clock is selected i/o port cmos input 12 (connections of on-chip pull-up resistor specified by software: 7) cmos input/output 12 (connections of on-chip pull-up resistor specified by software) n-ch open-drain 8 (on-chip pull-up resistor 8 (on-chip pull-up resistor 8 (no mask option) input/output specified by mask option) specified by mask option) withstand voltage is 13 v withstand voltage is 10 v withstand voltage is 13 v total 32 timer 3 channels 4 channels ? 8-bit timer/event counter ? 8-bit timer/event counter 0 (watch timer output added) ? 8-bit basic interval timer ? 8-bit timer/event counter 1 (can be used as a 16-bit timer/ ? watch timer event counter) ? 8-bit basic interval timer/watchdog timer ? watch timer a/d converter ? 8-bit resolution x 8 channels ? 8-bit resolution x 8 channels (successive approximation) (successive approximation) ? can operate at the voltage ? can operate at the voltage from v dd = 1.8 v from v dd = 2.7 v clock output (pcl) f , 524, 262, 65.5 khz ? f , 1.05 mhz, 262 khz, 65.5 khz (main system clock: (main system clock: during 4.19-mhz operation) during 4.19-mhz operation) ? f , 1.5 mhz, 375 khz, 93.8 khz (main system clock: during 6.0-mhz operation) buzzer output (buz) 2, 4, 32 khz ? 2, 4, 32 khz (main system clock: (main system clock: during 4.19-mhz operation or during 4.19-mhz operation subsystem clock: during 32.768-khz operation) or subsystem clock: during ? 2.93, 5.86, 46.9 khz 32.768-khz operation) (main system clock: during 6.0-mhz operation) serial interface 3 modes supported 2 modes supported ? 3-wire serial i/o mode ? 3-wire serial i/o mode...msb/lsb first selectable ...msb/lsb first selectable ? 2-wire serial i/o mode ? 2-wire serial i/o mode ? sbi mode vectored interrupt 3 external, 3 internal 3 external, 4 internal test inputs 1 external, 1 internal power supply voltage v dd = 2.7 to 6.0 v v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 ?c package ? 42-pin plastic shrink dip ? 42-pin plastic shrink dip (600 mil, 1.778-mm pitch) (600 mil) ? 44-pin plastic qfp ? 42-pin plastic shrink sop (375 mil, 0.8-mm pitch) (10 x 10 mm) note under development m pd75p0076 55 appendix b development tools the following development tools are provided for system development using the m pd75p0076. in the 75xl series, the common relocatable assembler of the series is used together with device files according to the product. ra75x relocatable assembler host machine order code (part no.) os supply medium pc-9800 series ms-dos tm 3.5" 2hd m s5a13ra75x ver.3.30 to 5" 2hd m s5a10ra75x ver.6.2 note ibm pc/at tm refer to os for 3.5" 2hc m s7b13ra75x or compatible ibm pcs 5" 2hc m s7b10ra75x device file host machine order code (part no.) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13df750068 ver.3.30 to 5" 2hd m s5a10df750068 ver.6.2 note ibm pc/at refer to os for 3.5" 2hc m s7b13df750068 or compatible ibm pcs 5" 2hc m s7b10df750068 note ver. 5.00 or later include a task swapping function, but this software is not able to use that function. remark operation of the assembler and device file is guaranteed only when using the host machine and os described above. prom write tools hardware pg-1500 this is a prom programmer which enables you to program a single-chip microcontroller with on-chip prom by stand-alone or host machine operation by connecting an attached board and a programmer adapter (sold separately). in addition, typical proms in capacities ranging from 256 k to 4 m bits can be programmed. pa-75p0076cu this is a prom programmer adapter dedicated for the m pd75p0076cu and 75p0076gt. it can be used when connected to a pg-1500. software pg-1500 controller pg-1500 and a host machine are connected by serial and parallel interfaces and pg-1500 is controlled on the host machine. host machine order code (part no.) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13pg1500 ver.3.30 to 5" 2hd m s5a10pg1500 ver.6.2 note ibm pc/at refer to os for 3.5" 2hd m s7b13pg1500 or compatible ibm pcs 5" 2hc m s7b10pg1500 note ver. 5.00 or later include a task swapping function, but this software is not able to use that function. remark operation of the pg-1500 controller is guaranteed only when using the host machine and os described above. m pd75p0076 56 debugging tools in-circuit emulators (ie-75000-r and ie-75001-r) are provided as program debugging tools for the m pd75p0076. various system configurations using these in-circuit emulators are listed below. hardware ie-75000-r note 1 the ie-75000-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75x or 75xl series products. for development of the m pd750068 subseries, the ie-75000-r is used with a separately sold emulation board (ie- 75300-r-em) and emulation probe. these products can be applied for highly efficient debugging when connected to a host machine and prom programmer. the ie-75000-r can include a connected emulation board (ie-75000-r-em). ie-75001-r the ie-75001-r is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75x or 75xl series products. the ie-75001-r is used with a separately sold emulation board (ie-75300-r-em) and emulation probe. these products can be applied for highly efficient debugging when connected to a host machine and prom programmer. ie-75300-r-em this is an emulation board for evaluating application systems that use the m pd750068 subseries. it is used in combination with the ie-75000-r or ie-75001-r in-circuit emulator. ep-750068cu-r this is an emulation probe for the m pd75p0076cu. when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. ep-750068gt-r this is an emulation probe for the m pd75p0076gt. ev-9500gt-42 when being used, it is connected with the ie-75000-r or ie-75001-r and the ie-75300-r-em. it includes a flexible board (ev-9500gt-42) to facilitate connections with target systems. software ie control program this program can control the ie-75000-r or ie-75001-r on a host machine when connected to the ie-75000-r or ie-75001-r via an rs-232-c or centronics interface. host machine order code (part no.) os supply medium pc-9800 series ms-dos 3.5" 2hd m s5a13ie75x ver.3.30 to 5" 2hd m s5a10ie75x ver.6.2 note 2 ibm pc/at refer to os for 3.5" 2hc m s7b13ie75x or compatible ibm pcs 5" 2hc m s7b10ie75x notes 1. this is a service part provided for maintenance purpose only. 2. ver. 5.00 or later include a task swapping function, but this software is not able to use that function. remarks 1. operation of the ie control program is guaranteed only when using the host machine and os described above. 2. the generic name for the m pd750064, 750066, 750068, and 75p0076 is the m pd750068 subseries. m pd75p0076 57 os for ibm pcs the following operating systems for the ibm pc are supported. os version pc dos tm ver.5.02 to ver.6.3 j6.1/v note to j6.3/v note ms-dos ver.5.0 to ver.6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only the english mode is supported. caution ver 5.0 and above include a task swapping function, but this software is not able to use that function. m pd75p0076 58 appendix c related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to device document name document no. english japanese m pd750064, 750066, 750068, 750064(a), 750066(a), 750068(a) data sheet u10165e note u10165j m pd75p0076 data sheet this document u10232j m pd750068 users manual u10670e u10670j m pd750068 instruction table iem-5606 75xl series selection guide u10453e u10453j note preliminary product information documents related to development tool document name document no. english japanese hardware ie-75000-r/ie-75001-r users manual eeu-1416 eeu-846 ie-75300-r-em users manual u11345e u11354j ep-750068gt-r users manual u10950e u10950j pg-1500 users manual eeu-1335 eeu-651 software ra75x assembler package users manual operation eeu-1346 eeu-731 language eeu-1363 eeu-730 pg-1500 controller users manual pc-9800 series eeu-1291 eeu-704 (ms-dos) base ibm pc series u10540e eeu-5008 (pc dos) base other related documents document name document no. english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j nec semiconductor device quality grades c11531e c11531j nec semiconductor device reliability and quality control c10983e c10983j electrostatic discharge (esd) test mem-539 semiconductor device quality assurance guide mei-1202 mei-603 microcontroller-related product guide third party products u11416j caution the contents of the documents listed above are subject to change without prior notice to users. make sure to use the latest edition when starting design. m pd75p0076 59 [memo] m pd75p0076 60 notes for cmos devices (1) precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. (2) handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. m pd75p0076 61 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8 m pd75p0076 ms-dos is a trademark of microsoft corporation. pc dos, pc/at, and ibm dos are trademarks of ibm corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited withou t governmental license, the need for which must be judged by the customer. the export or re-export of this product from a countr y other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 |
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